system verilog - How to Embed Systemverilog Interpreter using DPI-C?

Question

Problem Description:

I design in SystemVerilog and write the testbenches in the same language. I want to be able to compile my design and test different functions during simulation in the way you would using an interpreter with e. Ideally, I would have a terminal pop-up upon simulation when the simulator hit some line.

Potential Ideas:

I've looked at the DPI-C and it seems like I would have to "export" all tasks in my project in order to run them from the interpreter. However, I'm not sure how to do this automatically or if there's a better way. Furthermore, I have no idea how I would get C to open up a second shell for me to type the SystemVerilog tasks in (that I would want to run).

This is a problem echoes by my colleagues and it would make life a lot less painful to not have to wait 10 minutes between compiling just a testbench.

Answer 1

Hi i provide my two cents with another example.

EXAMPLE SV-CODE

 ////////////////////////////////////////////////////////////////////////
 //IMPORT FUNCTION DPI DECLARATION FROM C
 ////////////////////////////////////////////////////////////////////////            
import "DPI-C" function void python_sign_msg(string key_file_name, string msg_file_name, string signed_file_name );
import "DPI-C" function string return_string_in_c(string text, inout string output_txt);    
    

typedef class keycontrol_seq_handles;
//-----------------------
class keycontrol_predictor#(int PARAM_PLACEHOLDER = 1) extends pve_predictor#(keycontrol_seq_handles);//extends uvm_component;
………..
//////////////////////
//USE OF DPI
//////////////////////
string output_c,output2_c;
output_c = return_string_in_c("This text",output2_c);?
python_sign_msg("file.txt","bla","blo");

endclass