performance - Load/stores per cycle for recent CPU architecture generations

Question

Inspired by this answer to

FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2

what are the numbers of just-loads/loads-and-stores which one could issue on a core - for Sandy/Ivy Bridge, Broad/Haswell, Sky/Kaby Lake? Also interesting are the numbers of AMD Bulldozer, Jaguar and Zen.

PS - I know that might not be a sustainable rate because of cache/memory bandwidths, I'm only asking about issues.

Answer 1

Based on information from:

• http://users.atw.hu/instlatx64/
• http://www.agner.org/optimize/
• http://www.agner.org/optimize/blog/read.php?i=423
• https://en.wikichip.org/wiki/amd/microarchitectures/zen

Sandy/Ivy: per cycle, 2 loads, or 1 load and 1 store. 256bit loads and stores count double, but only with respect to the load or store itself - it still only has one address so the AGU becomes available again the next cycle. By mixing in some 256b operations you can still get 2x 128b loads and 1x 128b store per cycle.

Haswell/Broadwell: 2 loads and a store, and 256bit loads/stores don't count double. Port 7 (store AGU) can only handle simple address calculations (base+const, no index), complex cases will go to p2/p3 and compete with loads, simple cases may compete anyway but at least don't have to.

Sky/Kaby: the same as Broadwell

Bulldozer: 2 loads, or 1 load and 1 store. 256bit loads and stores count double.

Jaguar: 1 load or 1 store, and 256bit loads and stores count double. By far the worst one in this list, because it's the only low-power μarch in the list.

Ryzen: 2 loads, or 1 load and 1 store. 256bit loads and stores count double.