fpga - Verilog program for finding LCM of a number

Question

Hi so I have a school project to find the LCM of 2 4-bit numbers and I encounter some problems, I have the rough structure of the program out but couldn't complete the code please help :D. I'm using Vivado(vers.2019.2.1) and I'm programming a XC7A35TCPG236-1.

My program:)

module Mode4(
     input wire clk,
     output reg [3:0] an,
     output wire [0:7] seg,
     input wire [15:0] sw
    );
 wire [3:0] a, b;
 parameter MAX = 15 * 14;
 assign a = sw [1:0];
 assign b = sw [3:2];
 // Find the LCM of the two 4-bit number
 always@(*)
 [                  ]
 [                  ]
 [                  ]
 [                  ]
 reg [3:0] bcd, bcd0, bcd1, bcd2;
 
 always@(*) //convert LCM to BCD
 begin
 bcd0 = LCM % 10;
 bcd1 = [        ]
 bcd2 = [        ]
 end
 
 reg [1:0] mod4;
 always@(posedge clk)
    if (mod4 < 3) mod4 <= mod4 + 1;
    else mod4 <= 0;
    
    always@(*)
    case (mod4)
       0: an = 4'b1110;
       1: an = 4'b1101;
       2: an = 4'b1011;
       3: an = 4'b0111;
  endcase
endmodule 

question from:https://stackoverflow.com/questions/66059026/verilog-program-for-finding-lcm-of-a-number

Answer 1

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