Take a look at the example below. VECTOR_WIDTH is the number of bits in each std_logic_vector (12, in your case). FIFO_DEPTH is the number of vectors you want in your shift register.
library ieee;
use ieee.std_logic_1164.all;
entity vectors_fifo is
generic (
VECTOR_WIDTH: natural := 12;
FIFO_DEPTH: natural := 100
);
port (
clock: in std_logic;
reset: in std_logic;
input_vector: in std_logic_vector(VECTOR_WIDTH-1 downto 0);
output_vector: out std_logic_vector(VECTOR_WIDTH-1 downto 0)
);
end;
architecture rtl of vectors_fifo is
type fifo_memory_type is array (natural range <>) of std_logic_vector;
signal fifo_memory: fifo_memory_type(0 to FIFO_DEPTH-1)(VECTOR_WIDTH-1 downto 0);
begin
process (clock, reset) begin
if reset then
fifo_memory <= (others => (others => '0'));
elsif rising_edge(clock) then
fifo_memory <= input_vector & fifo_memory(0 to FIFO_DEPTH-2);
end if;
end process;
output_vector <= fifo_memory(FIFO_DEPTH-1);
end;
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