fpga - How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL?

Question

I am writing a code using VHDL to convert 24MHz and 12 MHz clock to 8 MHz clock. Can anyone please help me in this coding? Thanks in advance.

Answer 1

Is this for an FPGA? Or something else? Are you really dividing a clock, or just a signal? For a divide by three counter, try this link:

http://www.asic-world.com/examples/vhdl/divide_by_3.html

And for a 2/3:

http://www.edaboard.com/thread42620.html