xilinx - Vivado 2015.1 VHDL Input/ Output Violation

Question

I am getting through the tutorial of Nexys 4 DDR and I am implementing a simple MUX

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab1_2_1 is
    Port ( SW0 : in STD_LOGIC;
           SW1 : in STD_LOGIC;
           SW2 : in STD_LOGIC;
           LED0 : out STD_LOGIC);
end lab1_2_1;

architecture Behavioral of lab1_2_1 is

            Signal SW2_bar : STD_LOGIC;
            Signal SW0_int : STD_LOGIC;
            Signal SW1_int : STD_LOGIC;


begin
            SW2_bar <= not SW2;
            SW0_int <= SW0 and SW2_bar;
            SW1_int <= SW1 and SW2;
            LED0 <= SW0_int or SW1_int;

end Behavioral;

When I get to the part of generating a bitstream, I get this critical warning

NSTD #1 Critical Warning 1 out of 1 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: LED0.

and

UCIO #1 Critical Warning 1 out of 1 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: LED0.

Any Ideas?

Answer 1

Vivado expects you to define physical locations of the IOs and IO standards. IO standard depends on the voltage level and pull-up/pull-down resistors connected to pins of the FPGA.

You may add those into a constraint file (e.g. SDC or XDC). For example, I assigned output LED0 to pin A1 of the FPGA and defined the IO standard as 2.5V LVCMOS. The correct values can be found in the manual of your FPGA board.

set_property PACKAGE_PIN A1       [get_ports {LED0}];
set_property IOSTANDARD  LVCMOS25 [get_ports {LED0}];