sequential execution in process statement in vhdl

Question

for process statement in vhdl, it is said that the order of execution inside a process statement is sequential. My question is that, please look at the code below first, are a, b and c signals assigned to their new values concurrently or sequentially in if statement which is in process statement?

   process(clk) is
   begin
   if rising_edge(clk) then
   a <= b ;
   b <= c ;
   c <= a;
   end if;
   end process;

So if this is sequential, I must say that after the end of process, a is equal to b, b is equal to c and c is equal to b because we assigned b to a before we assigned a to c. However, this does seem not possible for hardware to do.

Answer 1

Constructing a Minimal, Complete, and Verifiable example containing your process:

library ieee;
use ieee.std_logic_1164.all;

entity sequent_exec is
end entity;

architecture foo of sequent_exec is
    signal a:       std_ulogic := '1';
    signal b, c:    std_ulogic := '0';
    signal clk:     std_ulogic := '0';
begin
    CLOCK:
    process
    begin
        wait for 10 ns;
        clk <= not clk;
        if now > 200 ns then
            wait;
        end if;
    end process;
DUT:
    process(clk) is
    begin
    if rising_edge(clk) then
    a <= b ;
    b <= c ;
    c <= a;
    end if;
    end process;
end architecture;

We see a, b and c shift values from one to another as a recirculating shift register:

Why that occurs is do to how VHDL's simulation cycle operates.

See IEEE Std 1076-2008

10.5 Simple Signal assignments (10.5.1 General):

A signal assignment statement modifies the projected output waveforms contained in the drivers of one or more signals (see 14.7.2), schedules a force for one or more signals, or schedules release of one or more signals (see 14.7.3).

A signal assignment queues a new value for signal update. How the projected output waveform queue is operated is described in 10.5.2.2 Executing a simple assignment statement:

Evaluation of a waveform element produces a single transaction. The time component of the transaction is determined by the current time added to the value of the time expression in the waveform element. For the first form of waveform element, the value component of the transaction is determined by the value expression in the waveform element.

An assignment without a time expression is to the current simulation time. (A delta cycle will occur - a simulation cycle without advancing the simulation time). The sequence of transactions described in 10.5.2.2 tell us old transactions to the same simulation time are deleted.

This means there's only one queue entry for any simulation time and explains why the last assignment to a particular signal is the one resulting in a transaction (and producing an event for a signal a process is sensitive to).

14.7 Execution of a model contains information about how a simulation cycle operates (14.7.5 Model execution).

14.7.5.1 General:

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

14.7.5.3 Simulation cycle describes the simulation cycle, the IEEE Std 1076-1993 is used here for simplicity not being cluttered with VHPI actions:

12.6.4 The simulation cycle

The execution of a model consists of an initialization phase followed by the repetitive execution of process statements in the description of that model. Each such repetition is said to be a simulation cycle. In each cycle, the values of all signals in the description are computed. If as a result of this computation an event occurs on a given signal, process statements that are sensitive to that signal will resume and will be executed as part of the simulation cycle.

At the beginning of initialization, the current time, Tc, is assumed to be 0 ns.

The initialization phase consists of the following steps:

-- The driving value and the effective value of each explicitly declared signal are computed, and the current value of the signal is set to the effective value. This value is assumed to have been the value of the signal for an infinite length of time prior to the start of simulation.

-- The value of each implicit signal of the form S'Stable(T) or S'Quiet(T)is set to True. The value of each implicit signal of the form S'Delayed(T) is set to the initial value of its prefix, S.

-- The value of each implicit GUARD signal is set to the result of evaluating the corresponding guard expression.

-- Each nonpostponed process in the model is executed until it suspends.

-- Each postponed process in the model is executed until it suspends.

-- The time of the next simulation cycle (which in this case is the first simulation cycle), Tn, is calculated according to the rules of step f of the simulation cycle, below.

A simulation cycle consists of the following steps:

a. The current time, Tc is set equal to Tn. Simulation is complete when Tn= TIME'HIGH and there are no active drivers or process resumptions at Tn.
b. Each active explicit signal in the model is updated. (Events may occur on signals as a result.)
c. Each implicit signal in the model is updated. (Events may occur on signals as a result.)
d. For each process P, if P is currently sensitive to a signal S and if an event has occurred on S in this simulation cycle, then P resumes.
e. Each nonpostponed process that has resumed in the current simulation cycle is executed until it suspends.
f. The time of the next simulation cycle, Tn, is determined by setting it to the earliest of

1. TIME'HIGH,
2. The next time at which a driver becomes active, or
3. The next time at which a process resumes.
4. If Tn = Tc, then the next simulation cycle (if any) will be a delta cycle.

g. If the next simulation cycle will be a delta cycle, the remainder of this step is skipped. Otherwise, each postponed process that has resumed but has not been executed since its last resumption is executed until it suspends. Then Tn is recalculated according to the rules of step f. It is an error if the execution of any postponed process causes a delta cycle to occur immediately after the current simulation cycle.

Signal values don't change during the execution of a process. Their updates are queued and applied in a different step in the execution of a simulation cycle.

back to -2008:

10. Sequential statements, 10.1 General

The various forms of sequential statements are described in this clause. Sequential statements are used to define algorithms for the execution of a subprogram or process; they execute in the order in which they appear.

We see the order of sequential signal assignment execution doesn't relate to the order signals are updated.