logic - why the D-FF does not use the clock assigned by me Quartus schematic

Question

The schematic given above is a simplified version of a design. But this is enough to explain my problem. As you can see from the schematic, clock signal of second dff is connected to (Q0' & clk). But in simulations, D1 is not using the signal connected to the port. Instead, it clearly uses my_clk signal. I added CLK1 pin for more clear observation. I wonder why does this happen? Also, I added the buffers at clock port with the hope of solving the problem but it didn't help. In case of someone offers to delete those buffers, it does not work. I also added more closer picture of the problematic area. I would really appreciate it if you explain me the problem here. Thanks in advance.

EDIT: When I remove the AND gates it works fine. So, the problem is the AND gate. But I need them in my overall design.

Answer 1

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