hdl - Parameter array in Verilog

Question

Is it possible to create a parameter array in Verilog? For example, anything like the following:

parameter[TOTAL-1 : 0] PARAM_ARRAY = {1, 0, 0, 2}

If it is not possible, what could be the alternative solution?

Answer 1

The given example is assigning unpacked values to packed parameter array. This in not allowed with Verilog.

Verilog only support simple vector based parameters. It does not support unpacked arrays. SystemVerilog, which superseded Verilog, does support parameter arrays. Almost all modern Verilog simulators are really SystemVerilog simulators (at least for the commercial simulators; open source simulators have incomplete support). To have your files read as SystemVerilog, change the file extension for .v to .sv. Then you can assign unpacked to a 2 dimensional parameter array:

parameter [7:0] PARAM_ARRAY [TOTAL-1 : 0]   = {8'd1, 8'd0, 8'd0, 8'd2};

Type names are also allowed. For example, using integer to creates a 32x4 array:

parameter integer PARAM_ARRAY [TOTAL-1 : 0]   = {1, 0, 0, 2};

This is documented in:

• IEEE Std 1364-2001 § 3.11 Parameters
• IEEE Std 1364-2005 § 4.10 Parameters
• (SystemVerilog) IEEE Std 1800-2012 § 6.20 Constants

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As a pure Verilog solution, you will need to created one long vector:

parameter [8*TOTAL-1:0] PARAM_ARRAY = {8'd1, 8'd0, 8'd0, 8'd2};

Then access with a slice as hard coded PARAM_ARRAY[7:0] or using the +:: PARAM_ARRAY[8*index +: 8]. Note that +: requires Verilog-2001 or higher (which even most open-source simulators support). Indexing vectors and arrays with +: