vhdl - When must a signal be inserted into the sensitivity list of a process

Question

I am confused about when a signal declared in an architecture must be inserted into the sensitivity list of a process.

Is there is a general law that can be followed in any situation?

I have real difficulties understanding when I have to include a signal in a process sensitivity list.

Answer 1

The "general law" is that

anything that your process needs to know about changes of needs to be in the sensitivity list.

---

For a typical synthesisable register with a synchronous reset:

process (clk) is
begin
    if rising_edge(clk) then
        if reset = '1' then
             -- do reset things
        else
             -- read some signals, assign some outputs
        end if;
    end if;
end process;

Only the clock needs to be in the list, as everything else is only looked at when the clock changes (due to the if rising_edge(clk) statement.

---

If you need an asynchronous reset:

process (clk, reset) is
begin
    if reset = '1' then
        -- do reset things
    elsif rising_edge(clk) then
        -- read some signals, assign some outputs
    end if;
end process;

then the reset signal must also be in the sensitivity list, as your design needs to check the value of it every time it changes, irrespective of what the clock is doing.

---

For combinatorial logic, I avoid using processes completely because of the problems keeping the sensitivity list up-to-date, and the potential for simulation then behaving differently to the synthesised code. This has been eased by the all keyword in VHDL-2008, but I still haven't found myself wanting to write long complicated combinatorial logic such that a process would help.