You won't find the information in the VHDL standard (IEEE Std 1076-2008), and what delta cycles do are not widely understood (there's a hint here about how much you actually need to know as a language user, an abstract knowledge can suffice).
Delta cycles precede VHDL. You can find references on the Internet dating back to 1971. VHDL gets it's delta cycles from the CONLAN BCL Time model where they are called steps (note we see interactive simulator commands to step today, see On the Origin of VHDL's Delta Delays, SUMIT GHOSH, Int. J. Engng Ed. Vol. 20, No. 4, pp. 638-645, 2004, and CONLAN Report, R. Piloty, M. Barbacci, D. Borrione, D. Dietmeyer, F. Hill, P. Skelly, Springer-Verlag 1983).
There's a simple reference explaining the concept in Ishiura Nagisa's PhD dissertation Studies on Logic Simulation and Hardware Description Languages where in Chapter 7 describing NES: A Nondeterministic Behavior Model for Hardware Description Languages.
7.2.2 Modeling of a Zero Delay
In designing hardware, timing relations among events are very important. HDL's must have a framework of specification of timing
relations. Thus one of the most important issues in developing a behavioral model of hardware is how to model time.
Probably one of the simplest way of modeling time is to represent a waveform by a sequence of symbols, each of which is associated with a minimum unit of the discrete time.
In VHDL terms these symbols are values of a type and discrete time is represented by a value of simulation time.
... Then the behavior of a hardware component is represented by a sequential machine over the set of the symbols. Although this modeling realizes simple mathematical handling, it lacks the ability to express the occurrence of multiple events at the same place within a unit time. So it is very difficult to explain the behavior of the circuits that contain loops consisting of zero delay components.
Simulating VHDL models produce a sequence of waveform events over simulation time. VHDL actually won't handle feedback loops with zero delay components at all. The point of Chapter 7 is to describe how to do so with an alternative HDL.
... Here, zero delay means the delay less than the unit time. It is a product of the quantitization of time. If the delay time of a component is less than the minimum unit of the time, it is specified as 0. The zero delay also comes up when we take a clock cycle as a unit time. In such a case, delay of gates is treated as zero delay because it is not measured by the unit time. The zero delay expresses before-after relationship or causality whose delay time is 0 measured by the unit time,
In VHDL simulation cycles that occur without the advancement of simulation time are delta cycles resulting from signal assignments with default incremental delays of 0. We can see that Jayaram Bhasker's description of delta cycles in A VHDL Primer (AT&T) is influenced by this passage. A VHDL Primer's description of delta cycles is widely quoted and still not enlightening, resulting in a search for writings of computer scientists on the subject.
Note that VHDL models operate by the resumption and subsequent re-suspension of processes in wait statements (a process with a sensitivity list has an implicit wait statement with the sensitivity list, as a the last statement of the process). Order of process execution resumption is not specified, VHDL can be simulated with processes running in parallel.
To deal with this signal updates are scheduled and don't take effect until all processes have suspended. If there are any updates scheduled for the current simulation time, the next simulation cycle is a delta cycle, otherwise simulation time is advanced to the next time a scheduled signal update occurs for the next simulation cycle. When there are no further events scheduled, simulation time advances to time'HIGH and simulation ends.
These delta cycles allow determinism in model execution where processes can execute in parallel by using signals that have history. Signals don't change during process execution, every process will execute identically every time. VHDL is formal notation intended to support formal verification of it's synthesis eligible subset, determinism is important here.
In order to deal with the zero delay, the time models of bcl (Conlan)[Pi183] and VHDL [Coe89] are designed on the basis of a sub-unit time named a step and a Δ-delay,
respectively. The signal value at a unit time is the final result of the infinite repetition of the computation in a step or a Δ-delay. Since these models are invented to compute the final result at
a unit time, no attention is paid to the order of the computation within a unit time. Actually, a step or a Δ-delay is associated with simulation under the unit delay model. There are cases where the final result depends on the order of the computation. For example, in Fig. 7.2, while the circuit is impractical, there may be a hazard on D which changes the signal value on Q. By using the models of bcl and VHDL, we will never get
this result. This is again because these languages are based on the
deterministic computation model.
This is not quite clear. Order of execution within successive delta cycles is determined by signal updates to the current simulation time. Delta cycles will occur in deterministic order.
The author goes on to expound the virtues of a nondeterministic behavioral model as an alternative and the remaining narrative here has little bearing on VHDL.
In addition to the non-determinism of the wholly theoretical model shown in Figure 7.2. VHDL can't deal with zero delay feedback loops. To catch these cases VHDL simulators implement a maximum number of delta cycles that are allowed before being simulation is stopped. While this number can sometimes be set via a command line option the [Coe89] reference (The VHDL Handbook by David R. Coelho of Vantage Analysis Systems in 1989) was in an era when the author's simulator started out with a delta cycle maximum of 127, reflecting simpler models and is bound to have increased over time. In modern simulators the default maximum is usually either 5,000 or 10,000 reflecting model complexity. The idea is to allow enough delta cycles to overcome model complexity without letting zero delay loops to run unbridled.
In Figure 7.2 if A, B, C and D are signals in VHDL where the inverter, buffer, and AND gate represent signal assignments with one delta delay (zero delay models), Signal D will not have a single delta cycle pulse (a glitch, smaller than measurable time). If you want a pulse you need delays, counting on the different in fall through times for the inverter and buffer.
When modeling with 0 delays VHDL can require additional signals as buffers to give delta delays or compensate for signals that have delta delays due to a different number of signal assignments in the logic path. On the other hand delays are ignored by synthesis (other than the occasional tool providing warnings).
So delta cycles using signal updates provide determinism for zero delay models - the correct results based on signal updates occurring after all processes are suspended. Without that determinism you'd be depending on order of assignment as in the use of variables. Using signals allows you to break up designs on arbitrary boundaries. Processes and other concurrent statements can be described without regard to order between them.
Precedence has a specific meaning in the standard (operator precedence), it's safer to say 'determinism'. You get the same answer every time because signal updates don't occur during process execution even for zero delay assignments.
