Recent articles tagged verilog

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verilog - What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?

posted Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - What is `+:` and `-:`?

posted Oct 17, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - I don't understand this define macro with replication

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - $fgetc SystemVerilog function doesn't read from stdin

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Why are "if..else" statements not encouraged within systemverilog assertion property?

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - For loop with binary numbers

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 4 bit register with enable and asynchronous reset

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Arbitrary Counter only displaying zeros

posted Oct 7, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

posted Mar 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - 如何编写Verilog以强制yosys / nextpnr输出手动设计的逻辑磁贴(How to write the verilog to force yosys / nextpnr to output a manually designed logic tiles)

posted Feb 21, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Writing random data to a RAM in a testbench

posted Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Passing packed data to a task to be compared with an unpacked data array for uvm constraints

posted Feb 19, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Parameterizing a SystemVerilog interface for optional array of a port element

posted Feb 6, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Functional Coverage - bin that collects all values that are not collected in other bins

posted Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Functional Coverage - bin that collects all values that are not collected in other bins

posted Jan 27, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - How can I automatically scale a $display column width?

posted Jan 25, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Does this SystemVerilog code have the wrong sequence of code?

posted Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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verilog - Does this SystemVerilog code have the wrong sequence of code?

posted Jan 24, 2021 in Technique[技术] by 深蓝 (71.8m points)

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